Abstract

An attempt is made to quantify the circuit complexity and mean circuit speed of linearly quantized straight PCM video encoding techniques. Any significant reduction in circuit complexity (i.e. the number of active and passive devices to be integrated) is considered important since this determines: chip area and yield if the encoder is to be fully integrated. Analysis indicates that the complexity of the more highly developed straight PCM video encoders can be reduced by typically a factor 3 using either non-programmed sequential encoding, pulse width modulator encoding or programmed sequential encoding (closed loop successive approximation). The encoder studied in this work is an 8-bit pulse width modulator video encoder using a 2-step production line technique and a detailed design procedure for a prototype encoder is given. This encoder is considered to achieve 7-bit resolution at a sampling rate of 13.3MHZ. A mathematical model of the encoder-decoder system is developed for numerical evaluation of the effect of encoder errors and white Gaussian noise upon a coded and decoded video signal. A triangular wave test is applied to examine the effect of encoder errors upon the statio transfer characteristic of the encoder. Dynamic errors are investigated by simulating colour subcarrier at the model input and observing the phase and gain errors at the filtered codec output. Using differential phase and gain, an attempt is made to determine a circuit design and alignment criterion such that most practical codecs will fall within specific bounds on these parameters (taken as ±6° and ±6% respective1y). In the absense of dither, Monte Carlo analysis indicates that the maximum voltage error incurred by each encoder error source should have a high probability (95%) of being less than a half quantum if 85 - 90% of codecs measured are to fall within the above bounds. If white Gaussian noise is used as a simple dither signal then the probability of a codec falling within the above bounds may increase to about 95%. Improvements to the encoder are discussed, including several automatic error correction techniques which combat instrumental errors and give a more robust PWM encoder. Also, by predetermining the most significant bit for each set of 4 coded bits it is possible to halve the encoder clock frequency (to 133MHZ) without significantly changing the encoder complexity.

Document Type

Thesis

Publication Date

1975-01-01

DOI

10.24382/4040

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