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dc.contributor.authorFuchs, Franz Xaver
dc.contributor.otherSchool of Engineering, Computing and Mathematicsen_US
dc.date.accessioned2013-10-24T12:57:47Z
dc.date.available2013-10-24T12:57:47Z
dc.date.issued2001
dc.identifierNOT AVAILABLEen_US
dc.identifier.urihttp://hdl.handle.net/10026.1/2354
dc.description.abstract

All MOS sample-and-hold circuits suffer to a greater or lesser extent from clock-feedthrough (CLFT), also called charge-injection. During the transition from sample to hold mode, charge is transferred from an MOS transistor switch onto the hold capacitor, thus the name charge-injection. This error can lead to considerable voltage change across the capacitor, and predicting the extent of the induced error potentials is important to circuit designers. Previous studies have shown a considerable dependency of CLFT on signal voltage, circuit impedances, clock amplitude and clock fall-time. The focus of this work was on the signal dependency of the CLFT error and on the CLFT induced signal distortion in open-loop sample-and-hold circuits. CLFT was found to have a strongly non-linear, signal dependent, component, which may cause considerable distortion of the sampled signal. The parameters influencing this distortion were established. It was discovered that distortion could be reduced by more than 20dB through careful adjustment of the clock fall-rate. Several circuit solutions that can help reduce the level of distortion arising from CLFT are presented. These circuits can also reduce the absolute level of CLFT. Simulations showed their effectiveness, which was also proven in silicon. The CLFT reduction methods used in these circuits are easily transferable to other switched-capacitor circuits and are suitable for applications where space is at a premium (as, for example, in analogue neural networks). A new saturation mode contribution to CLFT was found. It is shown to give rise to increased CLFT under high injection conditions.

en_US
dc.language.isoenen_US
dc.publisherUniversity of Plymouthen_US
dc.titleClock-Feedthrough Compensation in MOS Sample-and-Hold Circuitsen_US
dc.typeThesisen_US
dc.identifier.doihttp://dx.doi.org/10.24382/1341
dc.identifier.doihttp://dx.doi.org/10.24382/1341


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