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dc.contributor.authorCOUE, Dominique Xavier Henri Leon
dc.contributor.otherSchool of Engineering, Computing and Mathematicsen_US
dc.date.accessioned2013-09-10T11:14:10Z
dc.date.available2013-09-10T11:14:10Z
dc.date.issued1997
dc.identifierNOT AVAILABLEen_US
dc.identifier.urihttp://hdl.handle.net/10026.1/1633
dc.description.abstract

This thesis reviews various previously reported techniques for simulating artificial neural networks and investigates the design of fully-connected feedforward networks based on MOS transistors operating in the subthreshold mode of conduction as they are suitable for performing compact, low power, implantable pattern recognition systems. The principal objective is to demonstrate that the transfer characteristic of the devices can be fully exploited to design basic processing modules which overcome the linearity range, weight resolution, processing speed, noise and mismatch of components problems associated with weak inversion conduction, and so be used to implement networks which can be trained to perform practical tasks. A new four-quadrant analogue multiplier, one of the most important cells in the design of artificial neural networks, is developed. Analytical as well as simulation results suggest that the new scheme can efficiently be used to emulate both the synaptic and thresholding functions. To complement this thresholding-synapse, a novel current-to-voltage converter is also introduced. The characteristics of the well known sample-and-hold circuit as a weight memory scheme are analytically derived and simulation results suggest that a dummy compensated technique is required to obtain the required minimum of 8 bits weight resolution. Performance of the combined load and thresholding-synapse arrangement as well as an on-chip update/refresh mechanism are analytically evaluated and simulation studies on the Exclusive OR network as a benchmark problem are provided and indicate a useful level of functionality. Experimental results on the Exclusive OR network and a 'QRS' complex detector based on a 10:6:3 multilayer perceptron are also presented and demonstrate the potential of the proposed design techniques in emulating feedforward neural networks.

en_US
dc.language.isoenen_US
dc.publisherUniversity of Plymouthen_US
dc.titleFEEDFORWARD ARTIFICIAL NEURAL NETWORK DESIGN UTILISING SUBTHRESHOLD MODE CMOS DEVICESen_US
dc.typeThesis
plymouth.versionFull versionen_US
dc.identifier.doihttp://dx.doi.org/10.24382/4960
dc.identifier.doihttp://dx.doi.org/10.24382/4960


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