Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs
dc.contributor.author | Michail, HE | |
dc.contributor.author | Athanasiou, GS | |
dc.contributor.author | Kelefouras, Vasileios | |
dc.contributor.author | Theodoridis, G | |
dc.contributor.author | Stouraitis, T | |
dc.contributor.author | Goutis, CE | |
dc.date.accessioned | 2018-12-03T08:49:23Z | |
dc.date.available | 2018-12-03T08:49:23Z | |
dc.date.issued | 2016-04 | |
dc.identifier.issn | 0218-1266 | |
dc.identifier.issn | 1793-6454 | |
dc.identifier.other | ARTN 1650032 | |
dc.identifier.uri | http://hdl.handle.net/10026.1/12970 | |
dc.description.abstract |
<jats:p> High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided. </jats:p> | |
dc.format.extent | 1650032-1650032 | |
dc.language | en | |
dc.language.iso | en | |
dc.publisher | World Scientific Publishing | |
dc.rights | Attribution-ShareAlike 4.0 International | |
dc.rights | Attribution-ShareAlike 4.0 International | |
dc.rights | Attribution-ShareAlike 4.0 International | |
dc.rights | Attribution-ShareAlike 4.0 International | |
dc.rights | Attribution-ShareAlike 4.0 International | |
dc.rights.uri | http://creativecommons.org/licenses/by-sa/4.0/ | |
dc.rights.uri | http://creativecommons.org/licenses/by-sa/4.0/ | |
dc.rights.uri | http://creativecommons.org/licenses/by-sa/4.0/ | |
dc.rights.uri | http://creativecommons.org/licenses/by-sa/4.0/ | |
dc.rights.uri | http://creativecommons.org/licenses/by-sa/4.0/ | |
dc.subject | Hash function | |
dc.subject | message authentication code | |
dc.subject | pipeline | |
dc.subject | FPGA, security | |
dc.title | Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs | |
dc.type | journal-article | |
dc.type | Journal Article | |
plymouth.author-url | https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000369644500017&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=11bb513d99f797142bcfeffcc58ea008 | |
plymouth.issue | 04 | |
plymouth.volume | 25 | |
plymouth.publication-status | Published | |
plymouth.journal | Journal of Circuits, Systems, and Computers | |
dc.identifier.doi | 10.1142/S0218126616500328 | |
plymouth.organisational-group | /Plymouth | |
plymouth.organisational-group | /Plymouth/Faculty of Science and Engineering | |
plymouth.organisational-group | /Plymouth/Faculty of Science and Engineering/School of Engineering, Computing and Mathematics | |
plymouth.organisational-group | /Plymouth/REF 2021 Researchers by UoA | |
plymouth.organisational-group | /Plymouth/REF 2021 Researchers by UoA/UoA11 Computer Science and Informatics | |
plymouth.organisational-group | /Plymouth/Users by role | |
plymouth.organisational-group | /Plymouth/Users by role/Academics | |
dcterms.dateAccepted | 2015-10-09 | |
dc.identifier.eissn | 1793-6454 | |
dc.rights.embargoperiod | Not known | |
rioxxterms.versionofrecord | 10.1142/S0218126616500328 | |
rioxxterms.licenseref.uri | http://creativecommons.org/licenses/by-sa/4.0/ | |
rioxxterms.licenseref.startdate | 2016-04 | |
rioxxterms.type | Journal Article/Review |