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dc.contributor.authorMichail, HE
dc.contributor.authorAthanasiou, GS
dc.contributor.authorKelefouras, Vasileios
dc.contributor.authorTheodoridis, G
dc.contributor.authorStouraitis, T
dc.contributor.authorGoutis, CE
dc.date.accessioned2018-12-03T08:49:23Z
dc.date.available2018-12-03T08:49:23Z
dc.date.issued2016-04
dc.identifier.issn0218-1266
dc.identifier.issn1793-6454
dc.identifier.otherARTN 1650032
dc.identifier.urihttp://hdl.handle.net/10026.1/12970
dc.description.abstract

<jats:p> High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided. </jats:p>

dc.format.extent1650032-1650032
dc.languageen
dc.language.isoen
dc.publisherWorld Scientific Publishing
dc.rightsAttribution-ShareAlike 4.0 International
dc.rightsAttribution-ShareAlike 4.0 International
dc.rightsAttribution-ShareAlike 4.0 International
dc.rightsAttribution-ShareAlike 4.0 International
dc.rightsAttribution-ShareAlike 4.0 International
dc.rights.urihttp://creativecommons.org/licenses/by-sa/4.0/
dc.rights.urihttp://creativecommons.org/licenses/by-sa/4.0/
dc.rights.urihttp://creativecommons.org/licenses/by-sa/4.0/
dc.rights.urihttp://creativecommons.org/licenses/by-sa/4.0/
dc.rights.urihttp://creativecommons.org/licenses/by-sa/4.0/
dc.subjectHash function
dc.subjectmessage authentication code
dc.subjectpipeline
dc.subjectFPGA, security
dc.titleArea-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs
dc.typejournal-article
dc.typeJournal Article
plymouth.author-urlhttps://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000369644500017&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=11bb513d99f797142bcfeffcc58ea008
plymouth.issue04
plymouth.volume25
plymouth.publication-statusPublished
plymouth.journalJournal of Circuits, Systems, and Computers
dc.identifier.doi10.1142/S0218126616500328
plymouth.organisational-group/Plymouth
plymouth.organisational-group/Plymouth/Faculty of Science and Engineering
plymouth.organisational-group/Plymouth/Faculty of Science and Engineering/School of Engineering, Computing and Mathematics
plymouth.organisational-group/Plymouth/REF 2021 Researchers by UoA
plymouth.organisational-group/Plymouth/REF 2021 Researchers by UoA/UoA11 Computer Science and Informatics
plymouth.organisational-group/Plymouth/Users by role
plymouth.organisational-group/Plymouth/Users by role/Academics
dcterms.dateAccepted2015-10-09
dc.identifier.eissn1793-6454
dc.rights.embargoperiodNot known
rioxxterms.versionofrecord10.1142/S0218126616500328
rioxxterms.licenseref.urihttp://creativecommons.org/licenses/by-sa/4.0/
rioxxterms.licenseref.startdate2016-04
rioxxterms.typeJournal Article/Review


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